1. Field of the Invention
The present invention relates to an amplifier circuit having multiple gate field-effect transistors of improved adjustment of the operating point and improved control characteristics.
2. Description of the Related Art
Examples of multiple gate field-effect transistors (MG-FETs) are shown in FIG. 1. The setup of a respective transistor structure will be explained in greater detail with reference to the schematic illustration of FIG. 1.
In FIG. 1A, an MG-FET including three gate structures GS1, GS2 and GS3, a first region B1 connected to a first terminal S, and a second region B2 connected to a second terminal D is shown. The regions B1 and B2 are formed in a conventional manner in a semiconductor substrate, such as, for example, by suitably doped regions therein. A channel region K including a plurality of channel portions K1, K2 and K3 associated to the respective gate structures GS1, GS2 and GS3 is formed between the first region B1 and the second region B2. In the example shown in FIG. 1A, the first gate structure GS1 is connected to a first gate terminal G1 of the MG-FET, the second gate structure GS2 is connected to the first terminal S of the MG-FET and the third gate structure GS3 is connected to a second gate terminal G2 of the MG-FET.
Another example of an MG-FET is shown in FIG. 1B, the same reference numerals as in FIG. 1A being employed here. In contrast to the example shown in FIG. 1A, none of the gate structures is connected to a terminal according to FIG. 1B. Rather, the gate structures GS2 and GS3 are connected to each other and connected to the second gate terminal G2 of the MG-FET. The first gate structure GS1 is connected to the first gate terminal G1 of the MG-FET.
Since the MG-FETs according to FIG. 1 each comprise two gate terminals, they are also referred to as dual gate FETs (DG-FETs). It is, however, obvious to those skilled in the art that, apart from the configurations shown in FIG. 1, other FETs having only two gate structures or having more than three gate structures may be used. Also, any number of gate terminals, that is also more than two terminals, may be provided, wherein in this case the gate structures would have to be connected in a suitable way.
MG-FETs are used for amplifier circuits, wherein an input signal is received via one or several gate terminals (signal gate terminals) and a control signal with the help of which the gain of the amplifier circuit can be adjusted is received via one or several other gate terminals (control gate terminals). For tuners, the DG-FETs described above having only one signal gate terminal and one control gate terminal, which in this context are also referred to as tuner tetrodes or, in the case of an MOS-DG-FET, as MOS tuner tetrodes, are preferably employed. The operating point of such an amplifier circuit is adjusted using an auxiliary wiring integrated with the MG-FET on a chip. The function of this auxiliary wiring has a decisive impact on the control characteristic or the dependence of the gain of the MG-FET on the control voltage at the control gate terminals provided for this, which are also referred to as AGC gate terminals (AGC=automatic gain control).
The gain of the MG-FET or the amplifier circuit formed with it is a strictly monotonic increasing function with low and medium voltages at the control gate terminals of the MG-FET. In this region, the MG-FET may, for example, be operated together with an automatic gain control (AGC) increasing the amplification with small input signals and decreasing the amplification with large input signals, to obtain an output signal having a constant quantity or amplitude independently of the quantity of the input signal. The region of low and medium voltages at the control gate terminals of the MG-FET where the gain thereof is a strictly monotonic function, is also referred to as the AGC region. With higher voltages at the control gate terminal of the MG-FET, the amplification thereof is saturated since the portions of the channel of the MG-FET associated to the control gate terminals are completely open or formed. In this region, the gain of the MG-FET is largely constant, independently of the voltage at the control gate terminals of the MG-FET. The ideal and desired control characteristic of an amplifier circuit having an MG-FET features a transition between the AGC region and the saturation region, which is as smooth and soft as possible.
FIG. 2 shows an example of a conventional amplifier circuit 10. In this example, MG-FETs having a signal gate terminal and a control gate terminal, that is DG-FETs, are used. The amplifier circuit includes a first DG-FET or main DG-FET 20. The first DG-FET includes a signal gate terminal (gate 1) 22, a control gate terminal (gate 2) 24, a source terminal 26 and a drain terminal 28. In the example shown in FIG. 2, the setup and the wiring of the first DG-FET 20 are such that the signal gate terminal 22 and the control gate terminal 24 are associated to two portions of a channel via gate structures, as is shown in FIG. 1. We assume an exemplary configuration, as is shown in FIG. 1B. In this case, the gate structure GS1 is associated to the signal gate terminal 22 and thus to the channel portion K1. The gate structures GS2 and GS3 and thus the channel portions K2 and K3 are associated to the control gate terminal 24. The source terminal 26 is connected to the first region B1 and the drain terminal 26 is connected to the second region B2. Thus, a gate structure associated to the signal gate terminal 22 is arranged on the source side to the source terminal 26 and a gate structure associated to the control gate 24 is arranged on the drain side to the drain terminal 28. The first DG-FET 20 is arranged within a well in a substrate or directly in the substrate where the amplifier circuit 10 is formed. When the first DG-FET is an n-channel FET, the well is a p-well, when the first DG-FET is a p-FET, the well is an n-well. The well is preferably connected to the source 26 in an electrically conductive way.
The amplifier circuit 10 additionally comprises a second DG-FET 30 or an auxiliary DG-FET which preferably has a similar or identical setup to the first DG-FET 20. In particular, the second DG-FET 30 comprises a signal gate terminal 32, a control gate terminal 34, a source terminal 36 and a drain terminal 38 connected to the gate structures and regions as has been described above referring to the first DG-FET. Like in the first DG-FET, the signal gate terminal 32 is thus arranged on the source side and the control gate terminal 34 is arranged on the drain side. The well within which the second DG-FET 30 is arranged, in turn, is connected to the source 36.
The signal gate terminal 22 of the first DG-FET 20 and the signal gate terminal 32 of the second DG-FET 30 are connected to each other and connected to a signal input 42 of the amplifier circuit 10. The control gate terminal 24 of the first DG-FET 20 and the control gate terminals 34 of the second DG-FET 30 are connected to each other and connected to a control input 44 of the amplifier circuit 10. The source terminal 26 of the first DG-FET 20 and the source terminal 36 of the second DG-FET 30 are connected to each other and connected to a first exterior terminal (source) 46 of the amplifier circuit 10. The drain terminal 28 of the first DG-FET 20 is connected to a second exterior terminal (drain) 48 of the amplifier circuit 10. The drain terminal 38 of the second DG-FET 30 is connected to the signal gate terminal 32 of the second DG-FET 30 and thus, at the same time, connected to the signal gate terminal 22 of the first DG-FET 20 and the signal input 42 of the amplifier circuit 10.
The amplifier circuit 10 is usually operated by applying a direct voltage vdd from a supply voltage terminal 54 to the signal input 42 via a resistor 52, the voltage setting the operating point of the second DG-FET 30 and thus of the first DG-FET 20 with regard to the voltage at the signal gate terminal 22. At the same time, an (alternating current) input signal, such as, for example, an HF signal, from an input signal terminal 58 is coupled or applied capacitively to the signal input 42 of the amplifier circuit 10 via a capacitor 56. By the input signal, the resistance of a channel portion of the first DG-FET 20 associated thereto is controlled via the signal gate terminal 22 and also, with a voltage, applied from the outside, between the terminal 46 and the terminal 48, a current from the source terminal 26 through the channel of the first DG-FET 20 to the drain terminal 28. A control voltage is applied via the control input 44 to the amplifier circuit 10 and, in particular, to the control gate terminal 24 of the first DG-FET modulating the resistance of the portion of the channel of the first DG-FET 20 associated to the control gate terminal 22 and also the current between the source terminal 26 and the drain terminal 28. The control input 44 or the control voltage applied thereto is used to adjust or control the gain of the amplifier circuit 10. For this, the control voltage is usually only varied slowly.
The auxiliary wiring of the first DG-FET 20 by means of the second DG-FET 30 (auxiliary tetrode) illustrated with reference to FIG. 2 serves to adjust the operating point but has a serious practical disadvantage. When the gain is to be reduced starting from a saturation region, that is from a control voltage at the control input 44 where the amplifier circuit 10 has its maximum gain, by reducing the control voltage applied to the control input 44, the resistance of the portion of the channel of the second DG-FET 30 associated to the control gate terminal 34 increases since the control voltage is also applied to the control gate terminal 34. Thus, there is a higher voltage drop at the auxiliary tetrode or the second DG-FET 30 or between the source terminal 36 and the drain terminal 38 of the second DG-FET 30, this voltage in turn decreasing the resistance of that channel via the signal gate terminal 22 of the first DG-FET 20. This counteracts the intended reduction and results in an increase in the current between the source terminal 26 and the drain terminal 28 of the first DG-FET 20. In general, the decisive factor for the potential at the drain terminal 38 to decrease or increase with a decreasing potential at the control gate terminal 34 is the dimensioning of the second DG-FET (such as, for example, ratio of channel lengths, channel profiles, substrate control, etc.).
What is more, the channel portion of the second DG-FET 30 associated to the control gate terminal 34 is strongly controlled by the substrate potential since both portions of the channel of the second DG-FET 30 are arranged in one and the same well connected to the source terminal 36 of the second DG-FET 30. This problem could, however, be solved by a “dual well technology” (two separate wells), which would, however, entail considerable complexity as far as manufacturing is concerned.
Both effects described cause, when regulating the amplifier circuit 10 or reducing the gain of the amplifier circuit 10, a marked break in the gain characteristic at a control voltage or voltage Vg2 at the control gate terminals 24, 34 of the DG-FETs 20, 30 of Vg2=1.6 V, and a superelevation or excessive increase in the current between the source terminal 26 and the drain terminal 28 having a relatively abrupt onset. The break in the gain characteristic and the current superelevation are considerable disadvantages of the conventional amplifier circuit illustrated referring to FIG. 2.